Method to automatically add power line in channel between macros

ABSTRACT

A method includes detecting channels between macros in an integrated circuit. Each channel is associated with a region between two macros such that a shortest distance of the region satisfies a threshold value. The method also includes automatically adding at least one power line within at least one channel to satisfy a power integrity issue within the at least one channel. The power integrity issue is satisfied when two power lines having opposite polarity are coupled to provide power to a device within the at least one channel.

CLAIM OF PRIORITY

This application claims priority from and is a divisional application ofU.S. patent application Ser. No. 12/270,475, filed Nov. 13, 2008,entitled “METHOD TO AUTOMATICALLY ADD POWER LINE IN CHANNEL BETWEENMACROS,” the contents of which are incorporated by reference herein inits entirety.

FIELD OF THE DISCLOSURE

The present disclosure is generally directed to a method toautomatically add at least one power line with proper polarity or atleast two power lines with opposite polarities in a channel between atleast two macros.

BACKGROUND

Complex application-specific integrated circuit (ASIC) and/or a systemon a chip (SoC) designs use large numbers of hard macro cells, such asmemory cells and/or mixed-signal devices. The macros are generallyplaced in clusters due to timing and/or physical constraints. Theclustering of hard macro cells can be so large that signal delay on wireconnections to, from and/or through the macro cell clusters becomes ofconcern for ASIC/SoC performance. Gaps between pairs of macro cells maybe defined as channels when the gaps are smaller than certain thresholdvalues. Buffering in the channels is an efficient way to speed upsignals on wire connections. To enable buffering, the power gridintegrity in the channels should be guaranteed. The power grid integrityin a channel may mean that there should be at least two power supplylines with opposite polarities (one power line and one ground line)existing in that channel. Typically, the size of the channels (width forvertical channels or height for horizontal channels) between the macrocells is not large enough to satisfy the power grid integrityrequirement.

One conventional solution is to allocate larger channels to allow atleast two power lines with opposite polarities to be present in thechannels. However, this may lower the macro device placement density andtherefore increase the size of the die chip, which increases the cost ofthe final products. Another conventional solution is to manually patchindividual channels that are intended to be used. However, manualpatching is a time-consuming, tedious and error-prone process, and theresults may not be consistently repeatable.

SUMMARY

In a particular embodiment, a method is disclosed that includesdetecting channels between macros in an integrated circuit. Each channelis associated with a region between two macros such that a shortestdistance of the region satisfies a. threshold value. The method alsoincludes automatically adding at least one power line within at leastone channel to satisfy a power integrity issue within the at least onechannel. The power integrity issue is satisfied when two power lineshaving opposite polarity are coupled to provide power to a device withinthe at least one channel.

In another embodiment, an automated circuit design tool is disclosedthat includes a non-transitory processor-readable medium havingprocessor-executable instructions that are executable to cause aprocessor to detect channels between macros in an integrated circuit.Each channel is associated with a region between two macros such that ashortest distance of the region satisfies a threshold value. Theprocessor-executable instructions are also executable to cause theprocessor to automatically add at least one power line within at leastone channel to satisfy a power integrity issue within the at least onechannel. The power integrity issue is satisfied when two power lineshaving opposite polarity are coupled to provide power to a device withinthe at least one channel.

In another embodiment, an apparatus is disclosed that includes means fordetecting channels between macros in an integrated circuit. Each channelis associated with a region between two macros such that a shortestdistance of the region satisfies a threshold value. The apparatus alsoincludes means for automatically adding at least one power line withinat least one channel to satisfy a power integrity issue within the atleast one channel. The power integrity issue is satisfied when two powerlines having opposite polarity are coupled to provide power to a devicewithin the at least one channel.

In another embodiment, a computer-readable medium embodyingcomputer-readable data comprising a data file that represents a circuitdesigned using an automated circuit design tool is disclosed. Thecircuit includes a first channel between at least two macros disposed inthe circuit such that a shortest distance between the at least twomacros satisfies a threshold value. The circuit also includes a firstpower line that is automatically added in the first channel by anautomated circuit design tool in response to detecting a power integrityissue within the first channel. The power integrity issue is satisfiedby two power lines having opposite polarity being coupled to providepower to a device within the first channel.

In another embodiment, a circuit designed using an automated circuitdesign tool is disclosed. The circuit includes a first channel betweenat least two macros disposed in the circuit such that a shortestdistance between the at least two macros satisfies a threshold value.The circuit also includes a first power line that is automatically addedin the first channel by the automated circuit design tool in response todetecting a power integrity issue within the first channel. The powerintegrity issue is satisfied by two power lines having opposite polaritybeing coupled to provide power to a device within the first channel.

One particular advantage provided by the disclosed embodiments is that apower grid integrity in channels to enable buffering in the channels canbe accomplished by an automated design tool within regular machine runtime.

Another advantage provided by the disclosed embodiments is that theautomated design can be repeated with the same results consistently.

Other aspects, advantages, and features of the present disclosure willbecome apparent after review of the entire application, including thefollowing sections: Brief Description of the Drawings, DetailedDescription, and the Claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a particular illustrative embodiment of a systemhaving a power line with proper polarity added in a channel via anautomatic method;

FIG. 2 is a diagram of a particular illustrative embodiment of a systemhaving a power line with proper polarity added in a channel via anautomatic method and a device in the channel;

FIG. 3 is a diagram of a particular illustrative embodiment of a systemhaving two power lines with opposite polarities added in a channel viaan automatic method;

FIG. 4A is a diagram of a particular illustrative embodiment of a systemhaving a power line with proper polarity added in a horizontal channelvia an automatic method;

FIG. 4B is a diagram of a particular illustrative embodiment of a systemhaving multiple power lines added in a configuration that is notparallel to a horizontal channel via an automatic method;

FIG. 5 is a diagram of a particular illustrative embodiment of a systemto implement a method to automatically add a power line in a channel;

FIG. 6 is a flow diagram of a particular illustrative embodiment of amethod to automatically patch a power grid integrity issue within atleast one channel;

FIG. 7 is a diagram of a particular illustrative embodiment ofautomatically adding a power line in a vertical channel as well as in ahorizontal channel;

FIG. 8 is a diagram of a particular illustrative alternative embodimentof automatically adding a power line in a horizontal channel;

FIG. 9 is a flow diagram of a particular illustrative embodiment of amethod to automatically add a power line in a channel;

FIG. 10 is a flow diagram of another particular illustrative embodimentof a method to automatically add a power line in a channel;

FIG. 11 is a continuation of the flow diagram of FIG. 10;

FIG. 12 is a continuation of the flow diagrams of FIG. 10 and FIG. 1

FIG. 13 is a diagram of a particular illustrative embodiment of anautomated design tool to implement a method to automatically add a powerline in a channel;

FIG. 14 is a diagram of a particular illustrative embodiment of acircuit designed using a method to automatically add a power line in achannel; and

FIG. 15 is a block diagram of a communications device including devicesand circuits designed using a method to automatically add a power linein a channel.

DETAILED DESCRIPTION

Referring to FIG. 1, a diagram of a diagram of a particular illustrativeembodiment of a system having a power line added in a channel via anautomatic method is depicted and generally designated 100. A first macro110 may be disposed in a circuit adjacent a second macro 120. In aparticular embodiment, the first macro 110 and the second macro 120 maybe memory cells, mixed-signal devices, any other components of anapplication-specific integrated circuit (ASIC), a system on a chip(SoC), or any combination thereof. A channel 130 may be defined betweenthe first macro 110 and the second macro 120 whenever a shortestdistance 140 between the first macro 110 and the second macro 120 isbelow a threshold value. In a particular embodiment, the threshold valuemay be smaller than the pitch between adjacent system power supply lineswith opposite polarities in the power grid. A system power supply line150 may be disposed within the channel 130. A first power line 160 witha polarity opposite to the system power supply line 150 may beautomatically added in the channel 130 when less than two system powersupply lines 150 with opposite polarities are detected within thechannel 130 using a method to automatically add a power line to achannel, such as will be discussed with respect to FIGS. 6 and 9-12.

The method may include automatically detecting the number of powersupply lines in the channel 130, the polarities of the power supplylines in the channel, and then adding the first power line 160 withproper polarity in the channel 130 between at least two macros 110, 120when less than two system power supply lines 150 with oppositepolarities are detected within the channel 130. As used herein,“opposite” polarities indicate different voltages that are applied tothe power supply lines. As illustrative, non-limiting examples, apositive voltage may be opposite to a ground voltage, a negative voltagemay be opposite to a ground voltage, or a negative voltage may beopposite to a positive voltage, based on voltages that are used to powerthe ASIC/SoC. As used herein, a “proper” polarity of an automaticallyadded line when a line is detected in the channel (such as the line 150)is a polarity opposite to the polarity of the detected line. A “proper”polarity of an automatically added line when no lines are detected inthe channel (such as will be discussed with respect to FIG. 3) is anopposite polarity to another line that is automatically added to thechannel so that the two added lines have opposite polarities. The methodmay be implemented in circuit design software, automated designsoftware, a circuit design tool, an automated design tool, and the like.

By using an automatic method, the power grid integrity in channels toenable buffering in the channels can be accomplished by an automateddesign tool within regular machine run time. In addition, by using anautomatic method, the automated design can be repeated with the sameresults consistently.

Referring to FIG. 2, a diagram of a particular illustrative embodimentof a system having a power line added in a channel via an automaticmethod and a device in the channel is depicted and generally designated200. A device 202 may be disposed in the channel 130 between the macros110 and 120 and coupled to the system power supply line 150 and thefirst power line 160 in the channel 130. In a particular embodiment, thedevice 202 may be a decoupling capacitor, a substrate well connector, abuffer, or an inverter. The first power line 160 and the device 202 maybe automatically added according to the automatic method, such as willbe discussed with respect to FIGS. 6 and 9-12.

As depicted in the particular embodiments shown in FIG. 1 and FIG. 2,for example, at most the first power line 160 may be automatically addedin the channel 130 when one system power supply line 150 is detectedwithin the channel 130. The polarity of the first power line 160 shouldbe opposite to that of the system power supply line 150 to satisfy thepower grid integrity requirement. In the particular embodiments shown inFIG. 1 and FIG. 2, the first power line 160 will have a polarityopposite to a polarity of the one system power supply line 150 that isdetected within the channel 130. For example, if the polarity of thesystem power supply line 150 is positive (power), the polarity of thefirst power line 160 may be chosen to be ground. Similarly, if thepolarity of the system power supply line 150 is ground, the polarity ofthe first power line 160 may be chosen to be power (positive).

Referring to FIG. 3, a diagram of a particular illustrative embodimentof a system having two power lines with opposite polarities added in achannel via an automatic method is depicted and generally designated300. A second power line 360 with polarity opposite to the polarity ofthe first power line 160 may automatically be added in the channel 130when no system power supply lines are detected within the channel 130.

in a particular embodiment, the first power line 160 has the polarityopposite to the polarity of the second power line 360. For example, ifthe polarity of the first power line 160 is positive, the polarity ofthe second power line 360 will be chosen to be ground. Similarly, if thepolarity of the first power line 160 is ground, the polarity of thesecond power line 360 will be chosen to be positive. FIGS. 4A and 413depict alternative methods to automatically add a power line in ahorizontal channel.

Referring to FIG. 4A, a diagram of a particular illustrative embodimentof a system having a power line added in a horizontal channel via anautomatic method is depicted and generally designated 400. The systempower supply line 150 may be disposed within the horizontal channel 430,and a system power supply line 450 haying opposite polarity to thesystem power supply line 150 may be over a macro 120. The first powerline 160 with a polarity opposite to the polarity of the system powersupply line 150 may be automatically added in the horizontal channel 430between at least two macros 110, 120 when less than two system powersupply lines 150 with opposite polarities are detected within thehorizontal channel 430 using a method to automatically add a power lineto a channel.

In a particular embodiment, the method to automatically add a power lineto a channel may duplicate the methods of FIGS. 1-3, as applied tohorizontal channels. Although not shown in FIG. 4A, the method toautomatically add a power line to a channel may also include adding adevice disposed in the horizontal channel 430, similar to adding thedevice 202 in the vertical channel 130 between the macros 110 and 120,the device 202 coupled to the system power supply line 150 and the firstpower line 160 in the vertical channel 130, as shown in FIG. 2. Althoughnot shown in FIG. 4A, the method to automatically add a power line to achannel may include automatically adding a second power line in thehorizontal channel 430 when no system power supply lines are detectedwithin the horizontal channel 430, similar to automatically adding thesecond power line 360 in the vertical channel 130 when no system powersupply lines are detected within the vertical channel 130, as shown inFIG. 3.

Referring to FIG. 4B, a diagram of a particular illustrative embodimentof a system having multiple power lines added in a configuration that isnot parallel to a horizontal channel via an automatic method is depictedand generally designated 410. The method to automatically add a powerline to a channel may include automatically adding one or moreadditional power lines 460 that connect to a system power supply line450 not in the channel 430, the system power supply line 450 having thesame polarity as the additional power lines 460, the additional powerlines 460 extending into the channel 430. Some other additional powerlines 465 may also be automatically added that connect to another systempower supply line 455 not in the channel 430, the system power supplyline 455 having the same polarity as the additional power lines 465, theadditional power lines 465 extending into the channel 430. The polarityof the system power supply line 450 and the additional power lines 460is opposite to the polarity of the system power supply line 455 and theadditional power lines 465. The additional power lines 460 and 465 mayextend in a direction not parallel to the channel 430. In a particularembodiment, the system power supply lines 450 and 455 may be disposedabove the macro 120. In a particular embodiment, the system power supplylines 450 and 455 may be substantially parallel to the other systempower supply lines 150 and 470. The automatic method may further includedetecting the system power supply lines 450 and 455 to find out theirrespective polarities and locations. The power grid integrity of thehorizontal channel 430 may be accomplished with the additional powerlines 460 and 465.

In general, a power line may be automatically added to a channel, suchas in

FIGS. 1-3, 4A or 4B, after detecting the channel 130 or 430 between theat least two macros 110, 120 by determining that a shortest distance 140between the at least two macros 110, 120 is at most a threshold value.In a particular embodiment, the threshold value may be smaller than thesmallest value of the pitch between adjacent system power supply lineswith opposite polarities in the power grid.

Referring to FIG. 5, a diagram of a particular illustrative embodimentof a system to implement a method to automatically add a power line in achannel is depicted and generally designated 500. The system 500includes a device 502 that includes a processor 504 coupled to a memory506. The memory 506 includes automated design tool instructions 508,circuit detection instructions 510, and circuit tool instructions 512.The memory also includes a data file 518. The data file 518 includesthreshold values 514 and a circuit layout 516. The device 502 is coupledto an input device 530 and a display 550.

In operation, the processor 504 may be configured to access the circuitdetection instructions 510, the threshold values 514, and the circuitlayout 516 to detect whether there is a channel between at least twomacros. If a channel is detected between a first macro and a secondmacro, the processor 504 may be configured to access the circuitdetection instructions 510 and the circuit layout 516 to detect whetherthere are less than two system power supply lines with oppositepolarities within the channel. If there are less than two system powersupply lines with opposite polarities within the channel, the processor504 may be configured to access the automated design tool instructions508, the circuit tool instructions 512, and the circuit layout 516 toautomatically add a first power line with proper polarity in thechannel.

For example, the processor 504 may be configured to implement anautomatic method to add the first power line 160 in the channel 130,430as illustrated in FIG. 1 and FIG. 4A. The processor 504 may also beconfigured to implement an automatic method to add the device 202 in thechannel 130, as depicted in FIG. 2. When no system power supply linesare detected in the channel, the processor 504 may be configured toimplement an automatic method to add the first power line 160 and thesecond power line 360 in the channel 130, as shown in FIG. 3. Similarly,the processor 504 may be configured to implement an automatic method toadd the additional power line 460 to the system power supply line 450,where the additional power line 460 may extend in a direction notparallel to the channel 430, as illustrated in FIG. 4B.

Referring to FIG. 6, a diagram of a particular illustrative embodimentof a method to automatically patch a power grid integrity issue withinat least one channel is depicted and generally designated 600. Themethod 600 includes checking macros in an integrated circuit design forchannels between respective macros, as indicated at 602. For example,the integrated circuit may include the macros 110 and 120 and thechannel 130, as depicted in FIGS. 1-3. The method 600 includes detectingpower grid integrity issues within the channels, as indicated at 604.For example, the system power supply line 150 may be detected within thechannel 130, 430 as shown in FIGS. 1, 2, 4A, and 4B, or no system powersupply lines may be detected within the channel 130, as depicted in FIG.3. The method 600 includes automatically patching the power gridintegrity issue within at least one channel that lacks the power gridintegrity, as indicated at 606. For example, the first power line 160with proper polarity may be automatically added in the channel 130, 430as shown in FIGS. 1, 2, and 4A, or the first power line 160 and thesecond power line 360, which have opposite polarities, may beautomatically added in the channel 130, as depicted in FIG. 3.Alternatively, one or more additional power lines 460, 465 with oppositepolarities may be extended into the horizontal channel 430 in adirection that is not parallel to the horizontal channel 430 or thehorizontal system power supply lines 150, 450, 455, 470, as shown inFIG. 4B, for example.

The method 600 may further include determining whether the at least onechannel is a vertical channel, as in FIGS. 1-3, or a horizontal channel,as in FIGS. 4A and 4B. The method 600 may further include adding atleast one of a tap cell and a decoupling capacitor cell in the at leastone channel. For example, the device 202 may be added in the channel130, as shown in FIG. 2. The method 600 may further include connecting asystem power supply line disposed in an upper metal layer of theintegrated circuit with an additional power line disposed in a lowermetal layer of the integrated circuit, as will be discussed in furtherdetail with respect to FIG. 7. The method 600 may further includeconnecting a system power supply line disposed in an upper metal layerof the integrated circuit with at least one additional power linedisposed in a lower metal layer of the integrated circuit, as will bediscussed in further detail with respect to FIG. 8. The method 600 mayfurther include having at least one additional power line extend in adirection not parallel to a respective horizontal channel. For example,the additional power lines 460 and 465 may extend in a direction notparallel to the horizontal channel 430 shown in FIG. 4B.

Referring to FIG. 7, a diagram of a particular illustrative embodimentof automatically adding a power line in a vertical channel is depictedand generally designated 700. A substrate 702 of the integrated circuithas a lowest metal layer 704 disposed thereon, the lowest metal layer704 being designated the metal-1 or M1 layer. A first dielectricinsulating layer 706 is disposed on the lowest metal layer 704. A secondmetal layer 708 is disposed on the first dielectric insulating layer706. A second dielectric insulating layer 710 is disposed on the secondmetal layer 708. A third metal layer 712 is disposed on the seconddielectric insulating layer 710, the third metal layer 712 beingdesignated the metal-3 or M3 layer. A third dielectric insulating layer714 is disposed on the third metal layer 712. A fourth metal layer 716is disposed on the third dielectric insulating layer 714. A fourthdielectric insulating layer 718 is disposed on the fourth metal layer716. A fifth metal layer 720 is disposed on the fourth dielectricinsulating layer 718. A fifth dielectric insulating layer 722 isdisposed on the fifth metal layer 720. A sixth metal layer 724 isdisposed on the fifth dielectric insulating layer 722, the sixth metallayer 724 being designated the metal-6 or M6 layer. A sixth dielectricinsulating layer 726 is disposed on the sixth metal layer 724. A seventhmetal layer 728 is disposed on the sixth dielectric insulating layer726. In other illustrative embodiments, more alternating dielectricinsulating and metal layers may be added.

As illustrated in FIG. 7, a connection between the M6 layer 724 and theM3 layer 712 may be made through conductive vias 730 and 732. Theconductive vias 730 and 732 may be suitably insulated from theintervening metal layers 716 and 720. Automatically patching the powergrid integrity issue for a vertical channel may further includeconnecting a system power supply line disposed in an upper metal layerof the integrated circuit, such as the M6 layer 724 shown in FIG. 7,with an additional power line 160 (FIG. 1) disposed in a lower metallayer of the integrated circuit, such as the M3 layer 712 shown in FIG.7. In a particular embodiment, the conductive vias 730 and 732 may beused to connect a system power supply line disposed in an upper metallayer of the integrated circuit, such as the M6 layer 724 shown in FIG.7, with an additional power line disposed in a lower metal layer of theintegrated circuit, such as the M3 layer 712 shown in FIG. 7. Theconductive vias 730 and 732 may be used to automatically patch the powergrid integrity issue for the vertical channel.

The system power supply line 150 and the additional power lines 160 and360 shown in FIGS. 1-3 may be disposed in a lower metal layer of theintegrated circuit, such as the M3 layer 712 shown in FIG. 7, and may beconnected through the conductive vias 730 and 732 to system power supplylines (not shown in FIGS. 1-3) disposed in an upper metal layer of theintegrated circuit. such as the M6 layer 724 shown in FIG. 7.

The particular illustrative embodiment of automatically adding a powerline in a vertical channel depicted and generally designated 700 is alsoapplicable to the horizontal channel case, as shown in FIG. 4A. Thesystem power supply line 150 and the additional power line 160 shown inFIG. 4A may be disposed in an upper metal layer of the integratedcircuit, such as the M6 layer 724 shown in FIG. 7, and may be connectedthrough the conductive vias 730 and 732 to a system power supply line(not shown in FIG. 4A) disposed in a lower metal layer of the integratedcircuit, such as the M3 layer 712 shown in FIG. 7.

Referring to FIG. 8, a diagram of a particular illustrative alternativeembodiment of automatically adding a power line in a horizontal channelis depicted and generally designated 800. A substrate 802 of anintegrated circuit has a lowest metal layer 804 disposed thereon, thelowest metal layer 804 being designated the metal-1 or M1 layer. A firstdielectric insulating layer 806 is disposed on the lowest metal layer804. A second metal. layer 808 is disposed on the first dielectricinsulating layer 806. A second dielectric insulating layer 810 isdisposed on the second metal layer 808. A third metal layer 812 isdisposed on the second dielectric insulating layer 810, the third metallayer 812 being designated the metal-3 or M3 layer. A third dielectricinsulating layer 814 is disposed on the third metal layer 812. A fourthmetal layer 816 is disposed on the third dielectric insulating layer814. A fourth dielectric insulating layer 818 is disposed on the fourthmetal layer 816. A fifth metal layer 820 is disposed on the fourthdielectric insulating layer 818. A fifth dielectric insulating layer 822is disposed on the fifth metal layer 820. A sixth metal layer 824 isdisposed on the fifth dielectric insulating layer 822, the sixth metallayer 824 being designated the metal-6 or M6 layer. A sixth dielectricinsulating layer 826 is disposed on the sixth metal layer 824, seventhmetal layer 828 is disposed on the sixth dielectric insulating layer826, the seventh metal layer 828 being designated the metal-7 or M7layer. In other illustrative embodiments, more alternating dielectricinsulating and metal layers may be added.

In a particular embodiment, automatically patching the power gridintegrity issue for a horizontal channel may further include connectinga system power supply line disposed in an upper metal layer of theintegrated circuit, such as the M6 layer 824 shown in FIG. 8, with oneor more additional power lines 460 (FIG. 4B) disposed in a lower metallayer of the integrated circuit, such as the M5 layer 820 shown in FIG.8. The connection between the M6 layer 824 and the MS layer 820 may bemade through one or more conductive vias like conductive vias 834 and836, as shown in FIG. 8, for example. At least one additional power line460 disposed in the lower metal layer, such as the M5 layer 820, mayextend in a direction not parallel to a respective horizontal channel,as shown by the additional power lines 460, 465 in FIG. 4B. Theadditional power lines 460, 465 disposed in the M5 layer 820 may befurther connected to an even lower metal layer, such as the M3 layer812, through other conductive vias 830 and 832. The conductive vias 830and 832 may be suitably insulated from the intervening M4 layer 816.

Referring to FIG. 9, a flow diagram of a particular illustrativeembodiment of a method to automatically add a power line in a channel isdepicted and generally designated 900. The method 900 includes detectinga gap between two macros, such as the macros 110 and 120 of FIG. 1, asindicated at 902. The method 900 includes determining whether the gap issmaller than a threshold value, as indicated at 904. If the gap is notsmaller than a threshold value, then another macro is considered, asindicated at 910. If the gap is smaller than a threshold value, then achannel, such as the channel 130 of FIGS. 1-4A, has been detected. Themethod 900 includes detecting system power supply lines and theirpolarities, such as the system power supply line 150 of FIGS. 1-4A, inthe channel, as indicated at 906. The method 900 includes determiningwhether there are less than two system power supply lines with oppositepolarities in the channel, as indicated at 908. If there are not lessthan two system power supply lines with opposite polarities in thechannel, then another macro is considered, as indicated at 910. If thereare less than two system power supply lines 150 with opposite polaritiesin the channel 130, then a first power line 160 with proper polarityshould be added to the channel 130. The method 900 includes adding thefirst power line in the channel automatically, as indicated at 912.

The method 900 includes determining whether there is less than onesystem power supply line in the channel, as indicated at 914. If thereis not less than one system power supply line in the channel, thenanother macro is considered, as indicated at 910, If there is less thanone system power supply line 150 in the channel 130, then a second powerline 360 with a polarity opposite to the polarity of the first powerline 160 should be added to the channel 130. The method 900 includesadding the second power line in the channel automatically, as indicatedat 916. The method 900 includes considering another macro, as indicatedat 910. In a particular embodiment, the method 900 may be used toautomatically consider substantially all macros in an integratedcircuit.

Referring to FIGS. 10-12, a flow diagram of another particularillustrative embodiment of a method to automatically add a power line ina channel is depicted and generally designated 1000. The method 1000starts, as indicated at 1002, and includes scanning through all macrosin a circuit design, checking the top and right sides of each macro forchannels based on pre-defined widths and heights, channels on the topside being horizontal channels and channels on the right side beingvertical channels, as indicated at 1004. Channel heights correspond tohorizontal channels, while channel widths correspond to verticalchannels. The method 1000 includes inspecting the power/ground powergrid integrity in the channels, as indicated at 1006.

The method 1000 includes determining for vertical channels if at leastone pair of power/ground stripes (two power supply lines with oppositepolarities) exists in the vertical channel, as indicated at 1012 (as inthe particular illustrative embodiments shown in FIGS. 1-3). If at leastone pair of power/ground stripes exists in the vertical channel, thennothing more is done with that channel and another channel is considereduntil all the channels have been considered, as indicated at 1014. If atleast one pair of power/ground stripes does not exist in the verticalchannel, then the method 1000 includes determining whether one or noneof Vdd (power) and Vss (ground) exists in the vertical channel, asindicated at 1016. If neither Vdd nor Vss exists in the verticalchannel, then a pair of power/ground stripes are added automatically inthe vertical channel, as indicated at 1018 (as shown in FIG. 3), andthen another channel is considered until all the channels have beenconsidered, as indicated at 1038 in FIG. 12. If either Vdd or Vss existsin the vertical channel, then the opposite one (a power line withopposite polarity) is added automatically in the vertical channel, asindicated at 1020 (as shown in FIGS. 1-2), and then another channel isconsidered until all the channels have been considered, as indicated at1038 in FIG. 12.

The method 1000 includes determining for horizontal channels if at leasta pair of power/ground stripes exists in the horizontal channel, asindicated at 1008 (as in the particular illustrative embodiments shownin FIGS. 4A and 4B). If at least a pair of power/ground stripes existsin the horizontal channel, then nothing more is done with that channeland another channel is considered until all the channels have beenconsidered, as indicated at 1010. Referring to FIG. 11, if at least apair of power/ground stripes does not exist in the horizontal channel,then the method 1000 includes determining whether to use the M6 metallayer or the M5 metal layer to patch the horizontal channel, asindicated at 1022.

If the M6 metal layer is to be used, then the method 1000 includesdetermining whether one or none of Vdd and Vss exists in the horizontalchannel, as indicated at 1030 (as shown in FIG. 4A). If neither Vdd norVss exists in the horizontal channel, then a pair of power/groundstripes are added automatically in the horizontal channel, as indicatedat 1032, and then another channel is considered until all the channelshave been considered, as indicated at 1038 in FIG. 12. If either Vdd orVss exists in the horizontal channel, then the opposite one of Vdd Vssis added automatically in the horizontal channel, as indicated at 1034,and then another channel is considered until all the channels have beenconsidered, as indicated at 1038 in FIG. 12.

If the MS metal layer is to be used (as shown in FIG. 4B), then themethod 1000 includes cleaning up M5 metal layer stripes in thehorizontal channel (if applicable), as indicated at 1024. The method1000 includes querying the M6 metal layer power/ground bus over thebottom side macro to find the object, the x/y coordinates, and the widthof the M6 metal layer power/ground bus, as indicated at 1026, The method1000 includes querying the M5 metal layer power/ground bus inside thebottom side macro to find the object, the x/y coordinates, the width,and the pitch of the M5 metal layer power/ground bus, as indicated at1028. Referring to FIG. 12, the method 1000 includes creating M5 metallayer power/ground hook-up stripes between the M5 power/ground businside the bottom side macro and connecting the M5 metal layerpower/ground hook-up stripes to the M6 metal layer power/ground bus, asindicated at 1036. The M5 metal layer power/ground hook-up stripes mayextend into the horizontal channel in a direction not parallel to thehorizontal channel. The method 1000 includes considering another channeluntil all the channels have been considered, as indicated at 1038.

Referring to FIG. 13, a diagram of a particular illustrative embodimentof an automated circuit design tool to implement a method toautomatically add a power line in a channel is depicted and generallydesignated 1300. The automated circuit design tool 1300 may include aprocessor-readable medium having processor instructions that areexecutable to cause a processor to: scan a circuit to detect channels130 at a right side of a macro 110 (FIG. 1) and at a top of the macro110 (FIG. 4A) in the circuit, determine the number of system powersupply lines 150 and their polarities in the channels 130, andautomatically add a power line 160 with proper polarity in at least onechannel 130 where there are less than two system power supply lines 150with opposite polarities. A suitable processor may be the processor 504shown in FIG. 5, for example. In operation, the automated circuit designtool 1300 may effectively have a channel detector 1302 to scan a circuitto detect channels 130 at a right side of a macro 110 (FIG. 1) and at atop of the macro 110 (FIG. 4) in the circuit. The automated circuitdesign tool 1300 may also effectively have a system power supply linedetector 1304 to determine the number of system power supply lines 150and their polarities in the channels 130. The automated circuit designtool 1300 may also effectively have a power line adder 1306 toautomatically add a power line 160 with proper polarity in at least onechannel 130 where there are less than two system power supply lines 150with opposite polarities.

In a particular embodiment, the processor executable instructions arefurther executable to add one or more additional devices between a firstmacro 110 and a second macro 120. In this particular embodiment, theadditional devices between the first macro 110 and the second macro 120may include decoupling capacitors, substrate well connectors, buffers,inverters, or any combination thereof, as shown by the device 200 inFIG. 2, for example.

In a particular embodiment, the processor executable instructions arefurther executable to determine whether the at least one channel is avertical channel, as in FIG. 1, FIG. 2, and FIG. 3, or a horizontalchannel, as in FIG. 4A and FIG. 4B, for example. Where the channel is avertical channel, a first system power supply line disposed in a firstupper metal layer of an integrated circuit, such as the M6 layer 724shown in FIG. 7, may connect with a first added power line 160 (FIGS.1-3) disposed in a lower metal layer of the integrated circuit, such asthe M3 layer 712 shown in FIG. 7. Where the channel is a horizontalchannel, a second system power supply line disposed in a second uppermetal layer of an integrated circuit, such as the M6 layer 724 shown inFIG. 7, may connect with a second added power line 160 (FIG. 4A)disposed in a lower metal layer of the integrated circuit, such as theM3 layer 712 shown in FIG. 7. Alternatively, where the channel is ahorizontal channel, a second system power supply line disposed in asecond upper metal layer of an integrated circuit, such as the M6 layer824 shown in FIG. 8, may connect with one or more second added powerlines 460 (FIG. 4B) disposed in a lower metal layer of the integratedcircuit, such as the MS layer 820 shown in FIG. 8.

Referring to FIG. 14, a diagram of a particular illustrative embodimentof a circuit designed using a method to automatically add a power linein a channel is depicted and generally designated 1400. Acomputer-readable medium tangibly embodying computer-readable data mayinclude a data file, such as the data file 518 shown in FIG. 5, whichrepresents the circuit 1400 designed using an automated circuit designtool, such as the automated circuit design tool 1000 shown in FIG. 10.

The circuit 1400 may be designed using an automated circuit design tool.The circuit 1400 includes a first vertical channel 1402 between a firstpair of macros 1404, 1406 with a first patch 1407 disposed in the firstvertical channel 1402. The first patch includes at most one additionalpower line 1408 automatically added to the first vertical channel 1402.A first system power supply line 1410 is disposed in the first verticalchannel 1402. The circuit 1400 includes a second vertical channel 1412between a second pair of macros 1414, 1416 with a second patch 1417disposed in the second vertical channel 1412. The second patch 1417includes two additional power lines 1418, 1420 automatically added tothe second vertical channel 1412. The circuit 1400 includes a firsthorizontal channel 1422 between a third pair of macros 1404, 1414 with athird patch 1427 disposed in the first horizontal channel 1422. Thethird patch 1427 includes at most one additional power line 1428automatically added to the first horizontal channel 1422. A secondsystem power supply line 1430 is disposed in the first horizontalchannel 1422. The circuit 1400 includes a second horizontal channel 1432between a fourth pair of macros 1406, 1446 with a fourth patch 1437disposed in the second horizontal channel 1432. The fourth patch 1437includes two additional power lines 1438, 1440 automatically added tothe second horizontal channel 1432.

In a particular embodiment, the first patch 1407 and the second patch1417 may connect a system power supply line disposed in an upper metallayer of an integrated circuit, such as the M6 layer 724 shown in FIG.7, with at least one additional power line 1408, 1418 disposed in alower metal layer of the integrated circuit, such as the M3 layer 712shown in FIG. 7. In a particular embodiment, the third patch 1427 andthe fourth patch 1437 may connect a system power supply line disposed inan upper metal layer of an integrated circuit, such as the M6 layer 724shown in FIG. 7, with at least one additional power line 1428, 1438disposed in a lower metal layer of the integrated circuit, such as theM3 layer 712 shown in FIG. 7.

The circuit 1400 may include at least one device 1452 coupled to theadditional first power line 1448 in the channel 1442. In a particularembodiment, the at least one device 1452 may also be coupled to anadditional second power line 1450 in the channel 1442. In a particularembodiment, the at least one device 1452 is a decoupling capacitor, asubstrate well connector, a buffer, or an inverter.

FIG. 15 is a block diagram of a. communications device 1500 including amemory device that includes devices and circuits designed using a methodto automatically add a power line in a channel. The communicationsdevice 1500 includes a memory array of macro cells 1532 and a cachememory of macro cells 1564, which are coupled to a processor, such as adigital signal processor (DSP) 1510. The communications device 1500 alsoincludes a magneto-resistive random access memory (MRAM) device 1566that is coupled to the DSP 1510. In a particular example, the memoryarray of macro cells 1532, the cache memory of macro cells 1564, and theMRAM device 1566 include multiple macro cells, with devices and circuitsdesigned using a method to automatically add a power line in a channel,as described with respect to FIGS. 1-14.

FIG. 15 also shows a display controller 1526 that is coupled to thedigital signal processor 1510 and to a display 1528. A coder/decoder(CODEC) 1534 can also be coupled to the digital signal processor 1510. Aspeaker 1536 and a microphone 1538 can be coupled to the CODEC 1534.

FIG. 15 also indicates that a wireless controller 1540 can be coupled tothe digital signal processor 1510 and to a wireless antenna 1542. In aparticular embodiment, an input device 1530 and a power supply 1544 arecoupled to the on-chip system 1522, Moreover, in a particularembodiment, as illustrated in FIG. 15, the display 1528, the inputdevice 1530, the speaker 1536, the microphone 1538, the wireless antenna1542, and the power supply 1544 are external to the on-chip system 1522.However, each can be coupled to a component of the on-chip system 1522,such as an interface or a controller.

Those of skill would further appreciate that the various illustrativelogical blocks, configurations, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software, or combinationsof both. To clearly illustrate this interchangeability of hardware andsoftware, various illustrative components, blocks, configurations,modules, circuits, and steps have been described above generally interms of their functionality. Whether such functionality is implementedas hardware or software depends upon the particular application anddesign constraints imposed on the overall system. Skilled artisans mayimplement the described functionality in varying ways for eachparticular application, but such implementation decisions should not beinterpreted as causing a departure from the scope of Me presentdisclosure.

The steps of a method or algorithm described in connection with theembodiments disclosed herein may be embodied directly in hardware, in asoftware module executed by a processor, or in a combination of the two.A software module may reside in random access memory (RAM), flashmemory, read-only memory (ROM), programmable read-only memory (PROM),erasable programmable read-only memory (EPROM), electrically erasableprogrammable read-only memory (EEPROM), registers, hard disk, aretrievable disk, a compact disk read-only memory (CD-ROM), or any otherform of storage medium known in the art. An exemplary storage medium iscoupled to the processor such that the processor can read informationfrom, and write information to, the storage medium. In the alternative,the storage medium may be integral to the processor. The processor andthe storage medium may reside in an application-specific integratedcircuit (ASIC). The ASIC may reside in a computing device or a userterminal in the alternative, the processor and the storage medium mayreside as discrete components in a computing device or user terminal.

The previous description of the disclosed embodiments is provided toenable any person skilled in the art to make or use the disclosedembodiments. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the disclosure. Thus, the present disclosure is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope possible consistent with the principles andnovel features as defined by the following claims.

What is claimed is:
 1. A method comprising: detecting channels betweenmacros in an integrated circuit, wherein each channel is associated witha region between two macros such that a shortest distance of the regionsatisfies a threshold value; and automatically adding at least one powerline within at least one channel to satisfy a power integrity issuewithin the at least one channel, wherein the power integrity issue issatisfied when two power lines having opposite polarity are coupled toprovide power to a device within the at least one channel.
 2. The methodof claim 1, wherein the device is coupled to at least one of a macro orsignals propagating through the at least one channel.
 3. The method ofclaim 1, wherein the device is one of a decoupling capacitor to reducepower grid noise, a substrate well connector to prevent a latch-upviolation, a buffer to reduce a propagation delay of signals in the atleast one channel, or an inverter to reduce a propagation delay ofsignals in the at least one channel.
 4. The method of claim 1, furthercomprising detecting a power grid integrity within the channels prior toadding the at least one power line within the at least one channel. 5.The method of claim 1, wherein the at least one channel is a verticalchannel or a horizontal channel.
 6. The method of claim 5, wherein afirst system power supply line disposed in a first metal layer of theintegrated circuit connects with a first power line of the two powerlines, and wherein a second system power supply line disposed in asecond metal layer of the integrated circuit connects with a secondpower line of the two power lines.
 7. The method of claim 6, wherein thefirst power line and the second power line are disposed in a metal layerof the integrated circuit that is different than the first metal layerand the second metal layer.
 8. An automated circuit design toolcomprising a non-transitory processor-readable medium havingprocessor-executable instructions that are executable to cause aprocessor to: detect channels between macros in a circuit layout,wherein each channel is associated with a region between two macros suchthat a shortest distance of the region satisfies a threshold value; andautomatically add at least one power line within at least one channel tosatisfy a power integrity issue within the at least one channel, whereinthe power integrity issue is satisfied when two power lines havingopposite polarity are coupled to provide power to a device within the atleast one channel.
 9. The automated circuit design tool of claim 8,wherein the device is coupled to at least one of a macro or signalspropagating through the at least one channel.
 10. The automated circuitdesign tool of claim 8, wherein the device is one of a decouplingcapacitor to reduce power grid noise, a substrate well connector toprevent a latch-up violation, a buffer to reduce a propagation delay ofsignals in the at least one channel, or an inverter to reduce apropagation delay of signals in the at least one channel.
 11. Theautomated circuit design tool of claim 8, wherein theprocessor-executable instructions are further executable to cause theprocessor to detect a power grid integrity within the channels prior toadding the at least one power line within the at least one channel. 12.The automated circuit design tool of claim 8, wherein a first systempower supply line disposed in a first metal layer of the circuit layoutconnects with a first power line of the two power lines, and wherein asecond system power supply line disposed in a second metal layer of thecircuit layout connects with a second power line of the two power lines.13. The automated circuit design tool of claim 12, wherein the firstpower line and the second power line are disposed in a metal layer ofthe circuit layout that is different than the first metal layer and thesecond metal layer.
 14. An apparatus comprising: means for detectingchannels between macros in an integrated circuit, wherein each channelis associated with a region between two macros such that a shortestdistance of the region satisfies a threshold value; and means forautomatically adding at least one power line within at least one channelto satisfy a power integrity issue within the at least one channel,wherein the power integrity issue is satisfied when two power lineshaving opposite polarity are coupled to provide power to a device withinthe at least one channel.
 15. The apparatus of claim 14, wherein thedevice is coupled to at least one of a macro or signals propagatingthrough the at least one channel.
 16. The apparatus of claim 14, whereinthe device is one of a decoupling capacitor, a substrate well connector,a buffer, or an inverter.
 17. A non-transitory computer-readable mediumembodying computer-readable data comprising a data file that representsa circuit designed using an automated circuit design tool, the circuitcomprising: a first channel between at least two macro disposed in thecircuit such that a shortest distance between the at least two macrosatisfies a threshold value; and a first power line, wherein anautomated circuit design tool automatically added the first power linein the first channel in response to detecting a power integrity issuewithin the first channel, wherein the power integrity issue is satisfiedby two power lines having opposite polarity being coupled to providepower to a device within the first channel.
 18. The non-transitorycomputer-readable medium of claim 17, wherein the device is coupled toat least one of a macro or signals propagating through the firstchannel.
 19. The non-transitory computer-readable medium of claim 17,wherein the device is one of a decoupling capacitor, a substrate wellconnector, a buffer, or an inverter.
 20. A circuit designed using anautomated circuit design tool, the circuit comprising: a first channelbetween at least two macro disposed in the circuit such that a shortestdistance between the at least two macro satisfies a threshold value; anda first power line, wherein the automated circuit design toolautomatically added the first power line in the first channel inresponse to detecting a power integrity issue within the first channel,wherein the power integrity issue is satisfied by two power lines havingopposite polarity being coupled to provide power to a device within thefirst channel.
 21. The circuit of claim 20, wherein the device iscoupled to at least one of macro or signals propagating through thefirst channel.
 22. The circuit of claim 20, wherein the device is one ofa decoupling capacitor, a substrate well connector, a buffer, or aninverter.